Modern consumer electronics, such as smart phones, personal digital assistants, and location based services devices, as well as enterprise electronics, such as servers and storage arrays, are packing more integrated circuits into an ever shrinking physical space with expectations for decreasing cost. Every new generation of integrated circuits with increased operating frequency, performance and the higher level of large-scale integration have underscored the need for back-end integrated circuit manufacturing to provide more solutions involving the integrated circuit itself.
Numerous technologies have been developed to meet these requirements. Some of the research and development strategies focus on new package technologies while others focus on improving the existing and mature package technologies. Both approaches may include additional processing of the integrated circuits to better match the targeted package.
The continued emphasis in the package technology is to implement integration on the “z-axis,” that is, by stacking multiple chips in one package or by stacking one package on another package. This provides a dense chip structure having the footprint of a one-chip package. The cost of a stacked structure is only incrementally higher than the cost of a single die package and the assembly yields are high enough to assure a competitive final cost as compared to packaging the die in individual packages. The primary practical limitations to the general stacked structure approach are the low final yield and high testing cost.
For the multiple chips in one package approach, it is inevitable that some of the chip in the package will be defective to some extent, and therefore the final package test yield will be the product of the individual chip test yields, each of which is always less than one hundred percent. This can be particularly a problem even if only two chips are stacked in a package but one of them has low yield because of design complexity or technology.
For the package-on-package module approach, the problem is that the entire module can only be tested after the entire module is mounted on the printed circuit board. If either one package is faulty or the mounting process is faulty, the entire module has to be removed from the printed circuit board. This will inevitably increase the testing cost.
Still thinner, smaller, and lighter package designs and integrated circuit designs and printed circuit designs have been adopted in response to continuing requirements for further miniaturization. At the same time, users are demanding the entire system, including integrated circuit, packages and printed circuit board that are more reliable under increasingly severe operating conditions.
Thus, a need still remains for an integrated circuit package system providing low cost manufacturing, improved yield, improved reliability, and greater flexibility to offer more functionality and fewer footprints on the printed circuit board. In view of the ever-increasing need to save costs and improve efficiencies, it is more and more critical that answers be found to these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.